Clock Jitter in Communication Systems

For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces

Correlation Between EUT Failure Levels and ESD Generator Parameters

Some system-level electrostatic discharge (ESD) tests repeat badly if different ESD generators are used. For improving repeatability, ESD generator specifications have been changed, and modified generators have been compared in a worldwide round robin test. The test showed up to 1 : 3 variations of failure levels. Multiple parameters that characterize ESD generators have been measured. This paper correlates the parameters to test result variations trying to distinguish between important and nonrelevant parameters. The transient fields show large variations among different ESD generators. A correlation has been observed in many equipment under tests (EUTs) between failure levels and the spectral content of the voltage induced in a semicircular loop. EUT resonance enhances the field coupling, and is the dominate failure mechanism. The regulation on the transient field is expected to improve the test repeatability

Frequency-Domain Measurement Method for the Analysis of ESD Generators and Coupling

A method for analyzing electrostatic discharge (ESD) generators and coupling to equipment under test in the frequency domain is proposed. In ESD generators, the pulses are excited by the voltage collapse across relay contacts. The voltage collapse is replaced by one port of a vector network analyer (VNA). All the discrete and structural elements that form the ESD current pulse and the transient fields are excited by the VNA as if they were excited by the voltage collapse. In such a way, the method allows analyzing the current and field-driven linear coupling without having to discharge an ESD generator, eliminating the risk to the circuit and allowing the use of the wider dynamic range of a network analyzer relative to a real-time oscilloscope. The method is applicable to other voltage-collapse-driven tests, such as electrical fast transient, ultrawideband susceptibility testing but requires a linear coupling path

The Repeatability of System Level ESD Test and Relevant ESD Generator Parameters

Some system level ESD tests do not repeat well if different ESD generators are used. For improving the test repeatability, ESD generator specifications were considered to be changed and a world wide Round Robin test were performed in 2006 to compare the modified and unmodified ESD generators. The test results show the failure level variations up to 1:3 for an EUT among eight different ESD generators. Multiple ESD parameters including discharge currents and transient fields have been measured. This paper tries to find which parameters would predict the failure level the best in general. The transient fields show large variations among different ESD generators. The voltage induced in a semi-circular loop and the ringing after first discharge current peak show the best correlation to failure levels. The regulation on the transient field is expected to improve the test repeatability

Susceptibility Scanning as Failure Analysis Tool for System-Level Electrostatic Discharge (ESD) Problems

Susceptibility scanning is an increasingly adopted method for root cause analysis of system-level immunity sensitivities. It allows localizing affected nets and integrated circuits (ICs). Further, it can be used to compare the immunity of functionally identical or similar ICs or circuit boards. This paper explains the methodology as applied to electrostatic discharge and provides examples of scan maps and signals probed during immunity scanning. Limitations of present immunity analysis methods are discussed